Random and deterministic test generation methods, plus sequential circuit test generation.
The book describes on-chip decompression algorithms in Verilog, providing a realistic look at how these impact overall chip area and performance. Key Technical Coverage Digital System Test and Testable Design: Using ...
Gate-level faults, fault collapsing, and structural modeling in Verilog. Random and deterministic test generation methods
Are you interested in a specific from the book, like BIST or Boundary Scan , for a more detailed breakdown? Courses Syllabus – Monsoon 2024 - pgadmissions@iiit.ac.in like BIST or Boundary Scan